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E2C0034-27-Y5
Semiconductor MSC1162A
Semiconductor 40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
This version: Nov. 1997 MSC1162A Previous version: Jul. 1996
GENERAL DESCRIPTION
The MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch circuit, and 40-output circuit on a single chip. Display data is serially stored in the shift register at the rising edge of a clock pulse. Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to set the display blanking. Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel. The MSC1162A is compatible with the MSC1162.
FEATURES
* Logic Supply Voltage (VCC) : 5V * Driver Supply Voltage (VHV): 65V * Driver Output Current IOHVH1 (Only one driver output : "H") : -40mA IOHVH2 (All the driver outputs : "H") : -2mA IOHVL:1mA * Directly connected to VFD tube without pull-down resistors * Data Transfer Speed: 4MHz * Package : 60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK)
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Semiconductor
MSC1162A
BLOCK DIAGRAM
V HV V CC V CC CL CHG
LS DIN CLK C SI HVO1 PO1 I-1 O-1 HVO2 PO2 40-Bit Bidirectional Shift Register I-2 O-2
40-Bit Latch
HVO40 PO40 GND1 GND2 SO DOUT I-40 O-40
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INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic portion Input/Output Circuits and Driver Output Circuits Input Pin
VCC
VCC
INPUT
GND1
GND2
Output Pin
VCC
VCC
DOUT
GND2
GND1
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MSC1162A
VHV
VHV
Output
GND 1
GND 1
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PIN CONFIGURATION (TOP VIEW)
HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VHV GND 1 GND 2 CL NC LS NC R/L DIN VCC
,
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC : No-connection pin 60-Pin Plastic SSOP
MSC1162A
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
HVO 40 HVO 39 HVO 38 HVO 37 HVO 36 HVO 35 HVO 34 HVO 33 HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 24 HVO 23 HVO 22 HVO 21 VHV GND 1 GND 2 NC CHG NC CLK NC DOUT VCC
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PIN DESCRIPTION
Symbol CLK Type I Description Shift register clock input pin. Shift register reads data through DIN while the CLK pin is low state and the data in the shift register is shifted from one stage to the next stage at the rising edge of the clock. Serial data input pin of the shift register. Display data (positive logic) is input in through the DIN pin synchronization with clock. Serial data output pin of the shift register. Data is output through the DOUT pin in synchronization with the CLK signal. When R/L = High, the data of PO40 in the shift register is output through the DOUT pin. When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin. Latch strobe input pin When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS goes from high to low, the parallel output data (PO1-40) of the shift register is held. Clear input pin with a built-in pull-up resistor The CL pin is normally being set high. If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high irrespective of the states of the latch outputs. If the CL pin is set low, the driver outputs are driven low irrespective of the states of the CHG pin and latch outputs. This allows display blanking to be set. Input for testing (with a pull-down resistor) The CL pin is normally being set low. If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low irrespective of the states of the latch outputs. If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the latch outputs. This provides the easy testing of all lights after final assembly. High voltage driver outputs for driving VFD tube The driver outputs are in phase with the corresponding latch outputs (O1 to O40). The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors. Power supply pin for driver circuits of VFD tube Power supply pin for logic GND pin for driver circuits of a VFD tube. (D-GND) Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND. GND pin for the logic circuits. (L-GND) Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.
DIN
I
DOUT
O
LS
I
CL
I
CHG
I
VHO1-40 VHV VCC GND1 GND2
O
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MSC1162A
ABSOLUTE MAXIMUM RATINGS
Parameter *1 Logic Supply Voltage Driver Supply Voltage *1, *2 Input Voltage *1 *1 Output Voltage Driver Driving Frequency Withstand Output Voltage *1, *2 Power Dissipation Package Thermal Resistance *3 Storage Temperature Symbol VCC VHV VIN VO fDRV VHVO PD Rj-a TSTG Condition Applicable to logic supply pin Applicable to driver supply pin Applicable to all input pins Applicable to data output pin Applicable to driver output pin Applicable to driver output pin Ta 25C Ta > 25C -- Rating -0.3 to +6.5 -0.3 to +70 -0.3 to VCC +0.3 -0.3 to VCC +0.3 0 to 15 -0.3 to VHV +0.3 860 145 -55 to +150 Unit V V V V kHz V mW C/W C
Notes: *1 Maximum Supply Voltage with respect to L-GND and D-GND *2 Permanent damage may be caused if the voltage is supplied over the rating value. *3 Package Thermal Resistance (between junction and ambient) The junction temperature (Tj) expressed by the equation indicated below should not exceed 150C. Tj=P Rj-a+Ta (P: Maximum power consumption)
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MSC1162A
RECOMMENDED OPERATING CONDITIONS
Parameter Logic Supply Voltage Driver Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Driver Output Current Low Level Driver Output Current CLK Frequency CLK Pulse Width Data Setup Time Data Hold Time Data Pulse Width Latch Probe Pulse Width Symbol VCC VHV VIH VIL IOHVH1 IOHVH2 IOHVL fCLK tw(CLK) tSU(D-CLK) th(CLK-D) tw(D) tw(LS) See timing diagram Condition Applicable to logic supply voltage pin Applicable to driver supply voltage pin Applicable to all input pins Applicable to all input pins Applicable to driver output pin Only one output is high All outputs are high Min. 4.5 10 3.6 -- -- -- -- -- 75 80 50 140 80 50 0 0 0 -- -- -- 2 2 -40 Max. 5.5 65 -- 1.1 -40 -2 1 4 -- -- -- -- -- -- -- -- -- -- -- 85 Unit V V V V mA mA mA MHz ns ns ns ns ns ns ns ms ms ms ms C
Applicable to all driver output pins
CLK-LS tsu(CLK-LS) Setup Time LS-CLK tsu(LS-CLK) LS-CHG tsu(LS-CHG) LS-CL Pulse Width CHG CL tsu(LS-CL) tw(CHG) tw(CL) Top
Operating Temperature
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC=4.5 to 5.5V, VHV=10 to 65V, Ta=-40 to +85C) Parameter Logic Supply Current Symbol ICC1 ICC2 IHV1 Driver Supply Current IHV2 No load VCC=5.5V No load VCC=5.5V Condition All input: Low All input: High, Ta=25C All input: Low All input: High Ta=25C VCC=5.5V, VIN=5.5V Inputs excluding CHG IIH VCC=5.5V, VIN=5.5V CHG input VCC=5.5V, VIN=0V Inputs excluding CL IIL VCC=5.5V, VIN=0V CL input Ta=25C IOH=-0.1mA IOL=0.1mA VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V IOH=-40mA IOH=-2mA IOL=1mA -- Min. -- -- Typ. 4.3 0.5 -- 2.45 -- -- -- -- 15 -- -- -- -- -- -- -- Max. 6.65 1.0 1.0 3.8 1 80 1 -80 -- -- -- 1.1 1.1 -- -- 3.0 mA mA mA mA mA mA mA pF V V V V V V V Unit
-1 5 -1 -5 -- 3.5 4.5 -- -- VHV-4 VHV-4 --
High Level Input Current
Low Level Input Current
Input Capacitance High Level Data Output Voltage Low Level Data Output Voltage High Level Driver Output Voltage Low Level Driver Output Voltage
CI VODH VODL VOHVH1 VOHVH2 VOHVL
AC Characteristics
(VCC=5V, VHV=65V, Ta=25C) Parameter CLK-DOUT Delay Time Delay Time Low to High Transit Time Low to High Delay Time High to Low Transit Time High to Low Symbol tPD tDLH tTLH tDHL tTHL Condition -- -- -- -- -- Min. -- -- -- -- -- Typ. -- 0.3 2.0 0.3 2.0 Max. 300 1.0 5.0 1.0 5.0 Unit ns ms ms ms ms
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TIMING DIAGRAM
Semiconductor
1/fCLK CLK T1/2 tsu(D-CLK) th(CLK-D) DIN tw(D) DOUT tsu(CLK-LS) LS tsu(LS-CHG) tw(CHG) CHG tsu(LS-CL) CL tDLH HVO (1, 2, 39, 40) tDLH tw(CL) tw(CL) tw(CHG) tw(LS) tsu(LS-CLK) tPD tPD T3/4 T39/40 T1/2 tw(CLK) T3/4
tDHL
tDHL
HVO (OTHERS)
MSC1162A
tTLH
tTLH
tTHL
tTHL
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MSC1162A
FUNCTIONAL DESCRIPTION
Function Table Shift register
Input CLK R/L X H H L L DIN X L H L H L H PO2n PO2n PO1n PO1n PO3n PO3n PO1 Shift Register Parallel Out PO2 Not changed PO38n PO38n PO40n PO40n PO39n PO39n L H PO39 PO40 Output DOUT Not changed PO40 PO40 PO1 PO1
X: Don't Care PO1n to PO40n : PO1 to PO40 data just before CLOCK rises.
Latch
Input LS I H H X: Don't Care, m: 1 to 40 Shift Register Parallel Out POm X L H Latch Output Om Not changed L H
Driver output
Input CL L H H H CHG X H L L Latch Output Om X X L H Driver Output HVOm L H L H
X: Don't Care, m: 1 to 40
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NOTES ON USE
1. Connect GND1 to GND2 externally to be an equal potential voltage. 2. The contents of the shift register are undefined when the power is applied. Therefore, unnecessary driver outputs may be driven high just after power-on, and the VFD tube may flicker. To avoid this, follow the procedures: 1) Apply the driver power supply after applying the logic power supply, with the CL pin remained low. 2) Start displaying by setting the CL pin high after in putting display data the shift register through the DIN pin.
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Semiconductor Test circuit
MSC1162A
20pF VCC VHV HVO1 1.5kW HVO2
65V
5.0V HVO40
GND1, 2
CHG
CLK
R/L
CL
DIN
DOUT
LS
30pF
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MSC1162A
PACKAGE DIMENSIONS
(Unit : mm)
SSOP60-P-700-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.21 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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